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Design and Implementation of a Memory-Efficient Hardware Accelerator for Event-Based Convolutional Neural Networks

Yi, Haoran (2025) Design and Implementation of a Memory-Efficient Hardware Accelerator for Event-Based Convolutional Neural Networks.

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Abstract:The growing need for real-time, low-power, and high-performance vision processing has fueled interest in event-based CNNs and specialized hardware accelerators. Dynamic Vision Sensors (DVS) offer advantages such as low power consumption, reduced latency, and high temporal resolution, but their asynchronous and sparse data pose computational challenges for deep learning models. This thesis presents a memory-efficient hardware accelerator optimized for event-driven CNNs. It employs event-based convolution and depth-first processing to minimize redundant computations and optimize memory usage. Quantization-aware training and fixed-point arithmetic enhance energy efficiency while preserving accuracy. Implemented as an ASIC, the accelerator achieves an inference latency of 1.80 ms for MNIST and 1.34 ms for the DVS 128 Gesture dataset, with a power consumption of 600 mW per inference. The classification accuracy reaches 95.73% for MNIST and 69.79% for DVS 128 Gesture. Comprehensive evaluations highlight significant improvements in latency, power efficiency, and throughput over CPU- and GPU-based approaches. This research advances real-time perception for applications such as autonomous driving, robotics, and neuromorphic computing, demonstrating the critical role of specialized accelerators in next-generation event-based deep learning.
Item Type:Essay (Master)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:53 electrotechnology, 54 computer science
Programme:Embedded Systems MSc (60331)
Link to this item:https://purl.utwente.nl/essays/105308
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