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Design and Characterization of HPSC and CMOS XOR2 Standard Cell in 22nm FDSOI

Spelt, H.J. (2025) Design and Characterization of HPSC and CMOS XOR2 Standard Cell in 22nm FDSOI.

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Full Text Status:Access to this publication is restricted
Embargo date:1 July 2032
Abstract:Standard cell design is central to the devel- opment of modern digital integrated circuits, particularly in energy-constrained environments such as IoT nodes and wearable electronics. As logic gates form the backbone of arithmetic and control logic, optimizing their performance and energy efficiency is essential. This work investigates the implementation of a hybrid pass transistor logic with static CMOS output (HPSC) and conventional CMOS XOR2 gate, adapted from a prior 65nm low-power static CMOS design, within a 22nm Fully Depleted Silicon-On-Insulator (FDSOI) process node. The unique properties of 22nm FDSOI, including reduced leakage, improved electrostatic control, and body biasing capabilities, make it a compelling candidate for energy-efficient design exploration. A custom XOR2 standard cell was designed and characterized post- layout using Cadence Virtuoso tools and compared against the reference library cell. Metrics such as average power, propagation delay, PDP, and EDP were evaluated across PVT corners. The proposed cell demonstrated up to 9.56% lower EDP, 5.01% lower average power and 2.42% lower delay in post-layout simulations, although boundary cell power overheads and layout constraints limited further improvements. These results indicate that hybrid logic styles such as HPSC remain promising for scaled technologies, but demand careful consideration of parasitics and toolchain compatibility in advanced nodes.
Item Type:Essay (Bachelor)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:53 electrotechnology
Programme:Electrical Engineering BSc (56953)
Link to this item:https://purl.utwente.nl/essays/107658
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