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Implementing and communicating with SHILS

Blumink, Remco (2008) Implementing and communicating with SHILS.

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Abstract:Simulation can be used to check whether a design complies to its specifications. Digital hardware designs must be simulated cycle-true, bit accurate to verify timing. Performing such simulations takes prohibitively long for large hardware designs, i.e. a 6x6 NoC design requires 29 hours for simulation. Simulation on an FPGA platform can be used to shorten the simulation time. However, a large hardware design can not be simulated in a single FPGA as a whole. To be able to simulate a large system using a single FPGA, the system is divided in sections (entities) that are simulated sequentially. The entities in homogeneous systems are identical, the required logic for an entity can be reused for all entities when the state of the entities can be extracted. For extraction, a tool is provided. The resulting simulator performs simulations on a Design Under Test (DUT) sequentially. To simulate a system in an FPGA, it must be supplied with stimuli and control. This thesis integrates the simulator in an FPGA design, referred to as SHILS. SHILS provides stimuli and control buffers, and a MMIO interface. SHILS is controlled by software in an embedded processor, it is a co-simulation system. In order to extend the capabilities of SHILS, a design is proposed to link MATLAB to SHILS. The design is based on Xilinx System Generator, which arranges the communication between the MATLAB model and SHILS over Ethernet.
Item Type:Essay (Master)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:54 computer science
Programme:Computer Science MSc (60300)
Link to this item:http://purl.utwente.nl/essays/58356
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