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CλasH : from Haskell to hardware

Baaij, C. (2009) CλasH : from Haskell to hardware.

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Abstract:	Functional hardware description languages are a class of hardware description languages that emphasize on the ability to express higher level structural properties, such a parameterization and regularity. Due to such features as higher-order functions and polymorphism, parameterization in functional hardware description languages is more natural than the parameterization support found in the more traditional hardware description languages, like VHDL and Verilog. We develop a new functional hardware description language, CλasH, that borrows both the syntax and semantics from the general-purpose functional programming language Haskell. In many existing functional hardware description languages, a circuit designer has to use language primitives that are encoded as data-types and combinators within Haskell. In CλasH on the other hand, circuit designers build their circuits using regular Haskell syntax. Where many existing languages encode state using a so-called delay element within the body of a function, CλasH specifications explicitly encode state in the type-signature of a function thereby avoiding the nodesharing problem most other functional hardware description languages face. To cope with the direct physical restrictions of hardware, the familiar dynamically sized lists found in Haskell are replaced with fixed-size vectors. Being in essence a subset of Haskell, CλasH inherits the strong typing system of Haskell. CλasH exploits this typing system to specify the dependently-typed fixed-size vectors, be it that the dependent types are ‘fake’. As the designers of Haskell never set out to create a dependently typed language, the fixed-size vector specification suffers slightly from limits imposed by the typing system. Still, the developed fixed-size vector library presents a myriad of functionality to an eventual circuit designer. Besides having support for fixed-size vectors, CλasH also incorporates two integer type primitives. CλasH can be used to develop more than just trivial designs, exemplified by the reduction circuit designed with it. The CλasH design f this reduction circuit runs only 50% slower than a hand-coded optimized VHDL design, even though this first generation CλasH compiler does not have any optimizations whatsoever. With the used FPGA resources being in the same order as the resources used by the hand-coded VHDL we are confident that this first-generation compiler is indeed well behaved. Much has been accomplished with this first attempt at developing a new functional hardware description language, as it already allows us to build more than just trivial designs. There are however many possibilities for future work, the most pressing being able to support recursive functions.
Item Type:	Essay (Master)
Faculty:	EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:	54 computer science
Programme:	Computer Science MSc (60300)
Link to this item:	https://purl.utwente.nl/essays/59482
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