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Feasability study of frequency doubling using a dual-edge method

Oortgiesen, R. (2010) Feasability study of frequency doubling using a dual-edge method.

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Abstract:The performance of integrated Frequency Synthesizers relies on a clean fixed reference frequency, which is usually derived from a crystal. Unfortunately, commercially cheap crystal oscillators are limited in the range from 20-50 MHz. In general, a higher reference frequency results in better noise performances for Frequency Synthesizers. Therefore it is desired to be able to double the reference frequency and at the same time preserving the clean crystal properties. This work examines the feasibility of a low power and low noise CMOS Frequency Doubler in CMOS IC-technology. Main target specifications are: -151 dBc/Hz phase-noise oor, 10 kHz thicker noise corner frequency and reference spurs at the synthesizer output should be smaller than -80 dBc, within a power budget of approximately 4 mW. Within this scope a Phase-Locked Loop (PLL) has been analyzed, which showed insufficient yield for successful realization of a frequency doubler that would meet the given demands. Next to a PLL, an alternative has been examined which relies on passing through the edges of the clean reference crystal. By combining both rising- and falling edges of the reference frequency (fref) into both rising edges, an output frequency of 2 x fref is obtained. Main drawback of this approach is static timing errors between adjacent periods that result from even-order distortion or duty-cycle error of the incoming reference frequency. This has been overcome by detecting the error and correcting it by means of a control loop. The system has been analyzed on system level, its behavior quantified, and implemented on circuit level.
Item Type:Essay (Master)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:53 electrotechnology
Programme:Electrical Engineering MSc (60353)
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