High IMFDR3 Switched-Capacitor Amplifier design in CMOS 65nm

Koster, Pieter A.J.M. (2011) High IMFDR3 Switched-Capacitor Amplifier design in CMOS 65nm.

Abstract:Due to the continuous feature size downscaling trend of integrated circuit (IC) technologies and their corresponding supply voltages realizing high dynamic range (DR) receiver (RX) front-ends becomes increasingly problematic. Therefore a new „mixer-first‟ receiver front-end is envisioned, in which the mixer (MIX) is directly connected to the antenna, instead of using a traditional receiver front-end, in which the mixer is preceded with a low noise amplifier (LNA) stage limiting the dynamic range. A proper subsequent amplifier (AMP) stage is however still lacking being the focus in this document. Since the mixer stage already limits the noise performance the initial focus is upon realizing a highly linear amplifier. Knowing the initial desire to design a highly linear amplifier an amplifier topology is proposed, the dominant distortion mechanism determined and an optimization for high linearity suggested. Regarding the noise also the dominant contributing mechanism and an optimization method are revealed. Both parameters are considered for complementary metal-oxide–semiconductor (CMOS) 65nm integrated circuit technology being the current design technology node. Regarding the already existing literature, uniqueness is found in applying capacitive- rather than resistive feedback, with high linearity as the dominant design consideration. Also the switched biasing inside the capacitive feedback network is uncommon, allowing different Op Amp input- and output common-mode (CM) voltages. Finally the majority of the research already available is for old integrated circuit technologies and this document may hence provide additional insights for upcoming technology design nodes. The obtained amplifier performance specifications are an input-referred third-order intercept point (IIP3) of 19.6dBm. An equivalent input-referred noise voltage (EIRNV) of 2.93nV/Hz (at 20MHz). A closed-loop (CL) gain (ACL) and bandwidth (BWCL) of 11.9dB respectively 88.5MHz with a power consumption of 11.2mW.
Item Type:Essay (Master)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:53 electrotechnology
Programme:Electrical Engineering MSc (60353)
Link to this item:http://purl.utwente.nl/essays/61316
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