University of Twente Student Theses


Analysis and design of an ADC for a spectrum analyzer

Bicker, P.I. (2011) Analysis and design of an ADC for a spectrum analyzer.

[img] PDF
Abstract:Cognitive radio requires a system that is capable of quickly sensing the spectrum for available frequencies. In order for such a system to work a spectrum analyzer is required. The spectrum analyzer must be capable of detecting strong and weak signals simultaneously. This re- quires a high linearity in combination with low noise. A design for a spectrum analyzer was proposed in [1]. The spectrum analyzer increases linearity by attenuating the received signal. However, attenuating the signal reduces the SNR. Cross-correlation is used to reduce the noise in the digital domain. The requirements of the ADC in the spectrum analyzer are different from a typical situation. The linearity requirement is an SFDR of at least 70dB, and in order to measure a wide spectrum at once, the bandwidth requirement is 20MHz. The input voltage swing is low as result of atten- uation. The quantization error can be reduced by cross-correlation. By reducing the resolution to 1 bit, the calculations during cross-correlation can be reduced, as multiplications become single gate operations. In order to reduce the resolution of the ADC, oversampling is re- quired. A well known oversampling architecture is the sigma delta, which makes use of noise shaping to push noise outside the band of interest. It was found that an oversampling rate of at least 12 times is required in order to meet system requirements. A higher order loop filter reduces the amount of noise in the band of interest, but instability introduces distortion components, making a first order architecture the preferable choice. In order to achieve a high bandwidth, a continuous time con- verter is the preferred choice. However, the required bandwidth is hard to achieve. In current literature only implementations that reach only halve the required bandwidth or lower are found. Another issue with sigma delta converters are idle tones. It was found that these tones can mostly be reduced by dithering, at the cost of additional noise. Because of a limited bandwidth and occurrence of tones and distortion, the sigma delta architecture is found to be less suited for a spectral analyzer. Nyquist converters require dithering in order to reduce non-linearities as result of quantization. When adding white noise to the input, a reso- lution of at least 7 bit is required in order to achieve the system require- ments for the spectrum analyzer. Several architectures are considered. Flash requires amplification of the input signal. Pipelined and successive approximation register converters do not required high voltage swings on the input. Pipelined converters require amplification in each stage, consuming both power and reducing the linearity. High speed SAR ar- chitectures are possible in current CMOS technology, and have both a very high efficiency and have sufficient linearity when the components are correctly dimensioned. A SAR ADC implementation is proposed, based on an existing de- sign. By adjusting capacitors and transistor sizes the requirements for the SA are met. Linearity issues in the original design are resolved by a lower input voltage swing. The final solution achieves the required 70dB SFDR. The bandwidth requirement of 20MHz can be achieved by re- designing the control logic. The DAC, sample and hold and comparator are already capable of reaching the required speed.
Item Type:Essay (Master)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:53 electrotechnology
Programme:Electrical Engineering MSc (60353)
Link to this item:
Export this item as:BibTeX
HTML Citation
Reference Manager


Repository Staff Only: item control page