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A DFT based synchronization scheme for chirped communication

Moll, René (2013) A DFT based synchronization scheme for chirped communication.

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Abstract:The goal of this thesis was to derive a synchronization algorithm for chirped wireless communication systems and provide a high level implementation of this algorithm. The main requirements were speed, accuracy and low power consumption. This work has been done to extend a chirped binary frequency shift-keying (BFSK) receiver developed at the Integrated Circuit Design, Computer Architectures and Embedded Systems and Short Range Radio chairs at the University of Twente. Based on chirp signal properties, an algorithm has been derived, utilizing the link between time and frequency due to the chirp signal. Mixing two chirp signals leads to two frequency components, their exact frequencies depending on the time offset between the two signals. To determine this time offset, two detection methods are investigated. The first method, positive negative detection (PND), searches for both frequency components, while the second method, maximum power detection (MPD), searches for the strongest frequency component. Next, mapping the algorithm onto hardware was simulated. Relevant parameters and their performance impact were investigated using an design space exploration, to achieve a high performance withminimal hardware requirements. Results show that in ninety percent of the simulations the synchronization error is within the system’s resolution, which is limited by the fast Fourier transform (FFT) resolution. While transmission power was kept at such a level that, to the receiver, the communication signal was buried under the noise floor. The final system consists of a 1 bit analog to digital converter (ADC), a 256 point FFT and uses the MPDmethod. The PNDmethod showed to be unsuitable, with a correct synchronization performance of only fifty-five percent. Impact on the communication performance, measured via bit error rate (BER) curves, shows a maximumloss of 1 dB in signal to noise ratio (SNR) performance with a data rate of 4 kHz, but can be reduced by increasing the bandwidth of the modulation scheme. The proposed algorithm and hardware meet the requirements for speed, accuracy and power requirements. Firstly, as the algorithm requires only one execution, for the duration of half a chirp period. And secondly, the accuracy of the system can be chosen such, that it does not impact the communication performance significantly. Furthermore, recommendations are presented on the type of chirp signals to use. Either one up or down chirp should be used for synchronization. While for communication purposes, a combination of both types should be used to avoid discontinuities in the carrier’s frequency, as these discontinuities, in combination with any synchronization errors, lead to loss of communication.
Item Type:Essay (Master)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:54 computer science
Programme:Computer Science MSc (60300)
Link to this item:http://purl.utwente.nl/essays/64544
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