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Synthesizable Specification of a VLIW Processor in the Functional Hardware Description Language CλaSH

Bos, J.C.H. (2014) Synthesizable Specification of a VLIW Processor in the Functional Hardware Description Language CλaSH.

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Abstract:Within the computer architecture for embedded systems (CAES) group at the University of Twente, CλaSH has been developed as a tool to compile Haskell to synthesizable VHDL. This allows specifying register transfer level descriptions in Haskell. In this project, it is investigated whether it is feasible to describe the state-of-the-art VLIW DSP Xentium processor (IP of Recore Systems) with CλaSH. We evaluate difficulties and advantages of hardware design with CλaSH, and we are in particular interested in whether Haskell language features can be exploited to realize a concise and clear specification of a non-trivial hardware architecture. We argue that the “ideology” of functional programming is suitable and natural in hardware specifications and that the CλaSH descriptions are concise and “elegant”. With CλaSH, emphasis shifts towards a more abstract and high-level description of functionality. The language that one uses influences design experience and the way one conceptualizes architectures. HDL research to aid human understanding is therefore worthwhile an effort. Moreover, abstractions become necessary to manage future complexity.
Item Type:Essay (Master)
Clients:
Recore Systems, Enschede, Netherlands
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:31 mathematics, 50 technical science in general, 53 electrotechnology, 54 computer science
Programme:Embedded Systems MSc (60331)
Link to this item:http://purl.utwente.nl/essays/66086
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