University of Twente Student Theses


Design and implementation of an analog-to-time-to-digital convertor

Broek, J.D.A. van den (2012) Design and implementation of an analog-to-time-to-digital convertor.

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Abstract:This thesis describes the design and implementation of an analog-to-digital converter (ADC) taking an uncommon two-step approach: a voltage-to-time converter (VTC) converts the analog input signal to a difference in time between two digital transitions. Subsequently, a time-to-digital converter (TDC) quantizes this time difference to yield the digital output code. The aim of the thesis was to investigate the fundamental advantages of such a topology and to demonstrate them by implementing a proof-of-concept. Since TDCs can be highly digital structures, this approach was expected to yield an architecture with a mostly digital structure and work flow, ensuring good portability to, and inherent improvement with, newer CMOS technology. Another possible advantage is that in many TDCs, conversion time can be traded for accuracy; such reconfigurability is not common in conventional ADCs. After a comprehensive study of TDC concepts, VTC concepts and existing analog-to-time-to-digital converters, a novel architecture is proposed. It comprises a free-running ring oscillator and associated digital logic to form the TDC and a start-voltage controlled single slope converter to form the VTC. A reference sampling mechanism is used for insensitivity to most low-frequency variations and noise sources. The VTC consists of multiple channels that make use of the TDC in an interleaved fashion, distributing the power consumption of the TDC over multiple conversions, which is beneficial to the system performance. The multiplechannel VTC can also operate as one channel with higher accuracy, demonstrating the reconfigurability aspect of the analog-to-time-to-digital converter. A proof of concept was largely implemented on transistor level in 140 nm CMOS. The implemented circuit is indeed highly digital and the analog parts implemented so far are carefully picked for technology scalability. Although the final figure-of-merit (FoM) of the system is about one order of magnitude from state-of-the-art, most aspects of the performance are dominated by the digital circuitry. Therefore, the architecture is expected to improve rapidly when the concept is ported to a newer CMOS technology.
Item Type:Essay (Master)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:54 computer science
Programme:Computer Science MSc (60300)
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