HW-SW co-Design of an On-Chip IJTAG Dependability Processor

Continuous technological advancement grows the complexity of a System-on-Chip (SoC), consequently testing and debugging needs to be done on-chip by employing embedded instrumentation devices known as embedded instruments. On the other side, some embedded instruments can also be used for maintaining life-time dependability after deployment. In 2014, IEEE 1687 Internal Joint Test Access Group (IJTAG) introduced a flexible and standardized way to access embedded instruments. The standard specified the access procedures to be written in Procedural Description Language (PDL). The emerging of IJTAG eases internal access into embedded instruments by using PDL for dependability purposes. Thus this approach requires an on-chip processor, so that the growing complexity only grows in the software part. Therefore this thesis proposes a hardware and software co-design of an on-chip IJTAG dependability processor. This processor executes a dependability application written in PDL to maintain life-time dependability of a circuit. The hardware design based on a single cycle 32 bits MIPS that offers a simplest and open source processor. The software design starts by designing PDL cross compiler for translating PDL code into MIPS machine code.