Analysis, optimization, and design of a SLAM solution for an implementation on reconfigurable hardware (FPGA) using CλaSH
Appel, R.N. and Folmer, H.H (2016) Analysis, optimization, and design of a SLAM solution for an implementation on reconfigurable hardware (FPGA) using CλaSH.
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|Abstract:||Simultaneous localization and mapping (SLAM) is a mathematical problem with a potentially heavy computational load which is usually solved on a large computational system. These systems consume much energy which is not ideal for mobile robots. A field programmable gate array (FPGA) is reconfigurable hardware could be more efficient in terms of energy compared to standard computer systems due to its parallel capabilities. The goal of this project is to develop a SLAM implementation on an FPGA to be more efficient in terms of energy and computation time. SLAM is realized using a laser range finder (LRF) + odometry as sensor input. CλaSH is used as a mathematical hardware specification language. The two main subjects are: Graph-based SLAM and iterative closest point (ICP). The SLAM algorithm used is called graph-based SLAM which is used to correct for errors that are found during loop closing. The graph-based SLAM algorithm uses a linear system to correct for these errors. The linear system is sparse and can be solved be systems that preserve the sparsity of the system. Sparse matrices often do not fit well on embedded hardware which is solved by structuring and restricting the data. Other vectors in the system are dense and storing them with the sparse notation is cumbersome. A hardware architecture that performs a linear solving method using a combination of sparse and dense data is used to perform SLAM with a limited amount of resources. (ICP) is used to find the transformation between two sensor observations (laser range scans) to determine the movement of the robot. The ICP algorithm contains; constructing correspondences, and minimizing the errors. Error minimization is done by solving a least square system with QR decomposition using Gram-Schmidt method. Regular structure of algorithm and data allowed a vector ALU architecture is design as a trade-off between time and area. Data is stored into blockRAMs. Results produced by the FPGA are slightly less accurate compared to a reference solution in MATLAB but has a performance increase per Joule of three orders of magnitude.|
|Item Type:||Essay (Master)|
|Faculty:||EEMCS: Electrical Engineering, Mathematics and Computer Science|
|Subject:||53 electrotechnology, 54 computer science|
|Programme:||Embedded Systems MSc (60331)|
|Link to this item:||http://purl.utwente.nl/essays/71550|
|Export this item as:||BibTeX|
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