University of Twente Student Theses
Design of a frequency dividing subsampling phase-locked loop
Geertsema, J.B. (2017) Design of a frequency dividing subsampling phase-locked loop.
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| Abstract: | In Ultra Low Power wireless systems it is crucial to generate clock signals with as low power consumption and phase noise as possible. The solution is generating the clock with an LC-oscillator that uses much less than 1mW of power. It can be beneficial to increase the frequency of this LC-oscillator from 2.5GHz to 5GHz, for a better power and noise trade-off. To arrive at the desired lower output frequency, a frequency divider is required that adds as little power consumption and noise as possible. This way a system is implemented with a better power and noise trade-off. This thesis describes the analysis, design and comparison of a low power frequency divider. For a reliable comparison, an analysis is done to find the existing divider with the lowest power consumption using estimations. This divider turned out to be a counter implemented with true single phase clocked flip-flops. The counter is simulated to find the power consumption, noise and bandwidth. Because the counter’s power increases with division ratio, a new topology is implemented that does not have this shortcoming; the dividing subsampling phase-locked loop. This subsampling phase-locked loop is designed aiming at low power consumption. Unfortunately, the phase noise and the power of the implemented subsampling phase-locked loop is worse than that of the benchmark counter. With an input frequency of 5GHz and an output frequency of 2.5GHz, the subsampling phase-locked loop has a phase noise of −116dBc/Hz, which is 27dB more than that of the counter divider. The subsampling phase-locked loop has a power consumption of 8.8µW, that is double the power consumption of the counter. However, it is expected when a division ratio higher than 2 is used, the sub-sampling phase-locked loop has a lower power consumption than the benchmark counter. |
| Item Type: | Essay (Master) |
| Faculty: | EEMCS: Electrical Engineering, Mathematics and Computer Science |
| Subject: | 53 electrotechnology |
| Programme: | Electrical Engineering MSc (60353) |
| Link to this item: | https://purl.utwente.nl/essays/73325 |
| Export this item as: | BibTeX EndNote HTML Citation Reference Manager |
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