University of Twente Student Theses
An Optimized Type I Noise-Canceling PLL with Background Calibration
Zanen, J.O.P. (2017) An Optimized Type I Noise-Canceling PLL with Background Calibration.
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| Abstract: | Oscillators are electric circuits responsible for generating time and frequency references. High frequency clock signals are commonly generated from up-converted crystal references, using a PLL. Recent developments in phase noise canceling PLLs have established a basis for generating high quality clock signals using low chip area ring oscillators. As phase noise canceling gives additional reduction of low frequency phase noise, the PLL bandwidth becomes more important than the low frequency noise suppression. This opens the possibility to use Type I PLLs for noise canceling. A Type I noise canceling PLL is designed with performance similar to that of a Type II system, but at a lower chip area and complexity. The PLL transfer is modeled as a function of only two parameters and a mathematical optimum is established, dictating the dynamic behavior for an optimized Type I noise canceling PLL. This sets a design guideline for future Type I noise canceling PLLs decreasing the design complexity even further. Noise canceler performance is limited by mismatch in the canceler path. To calibrate the noise canceler compensation gain, a cross-correlation based error detector is suggested and an integrating control loop is designed. This calibration method can reduce the calibration error to negligible levels in 2.3ms. Contrary to existing calibration methods for phase noise cancelers, the proposed method can calibrate for changes in supply voltage and temperature during operation. |
| Item Type: | Essay (Master) |
| Faculty: | EEMCS: Electrical Engineering, Mathematics and Computer Science |
| Subject: | 53 electrotechnology |
| Programme: | Electrical Engineering MSc (60353) |
| Link to this item: | https://purl.utwente.nl/essays/74327 |
| Export this item as: | BibTeX EndNote HTML Citation Reference Manager |
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