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Design of a 100 MHz bandwidth low noise linear voltage sensing baseband amplifier

Hulman, T. (2018) Design of a 100 MHz bandwidth low noise linear voltage sensing baseband amplifier.

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Abstract:With the introduction of Wi-Fi, Bluethooth, LTE and 5G in a smartphone the number of wireless on-chip receivers is rapidly increasing. Increasing the number of receiver chains costs chip area and power, which can be unwanted. Instead of using separate narrowband receivers per standard, one can also think about a exible wideband receiver system that is able to handle multiple wireless standards. A possible implementation for such a exible receiver is a mixer-�rst receiver that is able to receive a large bandwidth. The implementation of an LNA in such a system is not obvious, due to narrow-band noise and power matching constraints. Ampli�cation is in most cases moved to baseband, creating demand for baseband ampli�ers. This thesis focuses on the design of such a baseband ampli�er for a mixer-�rst receiver. Due to the absence of ampli�cation earlier in the chain the ampli�er has strict noise and linearity requirements together with high bandwidth. Ideally, the ampli�er is strictly voltage sensing to minimize signal loss on the interface between the ampli�er and preceding �lter stage. The ampli�er is implemented as a single stage inverter with a capacitive feedback network in GF 28 nm technology. The designed inverter achieves a gain of 17 dB with a bandwidth of 147 MHz. The input referred voltage noise at 100 MHz is equal to 700 pV= p (Hz). The linearity of the ampli�er is speci�ed with an IIP3 of -2.25 dBm. The power of the inverter is simulated at 1.48 mW. The performance of the ampli�er falls within the requirements for noise, bandwidth, power and input impedance, but gain and linearity are found too low. It is suspected that the linearity of the inverter can be increased, so to analyze the e�ect of nonlinearity on an baseband inverter stage, a distortion analysis is conducted. Expressions to describe Harmonic Distortion (HD) and Intermodulation (IM) distortion in a single MOSFET and inverter circuit are derived. The derived expression is checked against simulation results and individual distortion components have been identi�ed. The analysis revealed that, besides the traditional third order distortion by gm, gds and their cross terms, second order distortion is upconverted to third order distortion due to interaction with a �rst order term. It is also found that for a high output swing gds and third order cross terms dominate the nonlinearity of the inverter. It is shown that, for this speci�c implementation, an NMOS is more linear than an inverter. Also transistor length and operation region have a signi�cant in uence on the linearity performance of an inverter. Several other improvements have been proposed, such as canceling the second order distortion and increasing the loopgain of the inverter, as this will also increase linearity performance.
Item Type:Essay (Master)
Clients:
1993, Netherlands
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:50 technical science in general, 53 electrotechnology
Programme:Electrical Engineering MSc (60353)
Link to this item:http://purl.utwente.nl/essays/75080
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