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Approximate signed multipliers for multiply-accumulate circuits

Oedzes, J.M. (2018) Approximate signed multipliers for multiply-accumulate circuits.

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Abstract:The field of approximate computing studies the trade-off between cost and quality in approximate computation or storage circuits, where computational quality is traded for reduced cost in hardware. Approximate computing is particularly interesting for MAC circuits, as the accumulation allows for error balancing. This work investigates an 8 bit approximate hybrid signed multiplier design targeted at application in MAC circuits. Both an accurate design and the approximate design are modeled in both matlab and VHDL. The VHDL model is synthesized by Quartus for the Cyclone IV E FPGA, and the synthesis results are used for cost estimation in terms of the amount of logic elements. Different error metrics, for both uncorrelated and correlated input distributions are considered for quality analysis, using uniform and normal distributions. It appears that the approximate design only saves about 6% in hardware compared to an accurate design, but has zero average error for different kinds of input distributions.
Item Type:Essay (Bachelor)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:53 electrotechnology
Programme:Electrical Engineering BSc (56953)
Link to this item:http://purl.utwente.nl/essays/75243
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