Analysis and Design of a Dependability Manager for Self-Aware System-on-Chips

The Dependability Manager (DM) is a coprocessor for SoCs that employs reconfigurable scan networks (RSN) to increase the dependability of the chip. The DM features a novel Retargeting Engine and Interrupt Management Unit to access IEEE 1687 (IJTAG) RSNs. A toolchain was developed to integrate PDL procedures into the dependability application. The architecture was proven in simulations and on a Cyclone IV FPGA.