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Optimizing FPGA Designs for Maximum Throughput using RapidWright

Kruiper, T.R. (2019) Optimizing FPGA Designs for Maximum Throughput using RapidWright.

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Abstract:Nowadays the number of resources inside a field-programmable gate array (FPGA) are rapidly increasing. This opens up new research fields, because most designs wont use all the resources a FPGA has to offer. These extra resources can be used for several applications, e.g. increasing security or improving throughput. This research looks into the possibility to use the extra resources to increase throughput of FPGA designs. Throughput in a FPGA design goes hand in hand with the frequency at which the FPGA is running, being able to run the FPGA at a higher frequency results in a higher throughput. The limiting factor of the maximum frequency is the combinational logic and routing delays. By adding registers in between the logic these delays are reduced, which in turn increases the maximum frequency and thus increases the throughput. This method is called pipelining. In this thesis an automatic approach to add pipeline stages is developed, instead of manually adapting the design. The Java tool RapidWright is used which allows for editing the netlist and is a perfect tool to do CAD for FPGAs. The algorithm is tested on several designs and it is shown that it does indeed improves the maximum frequency of FPGA designs up to 35% depending on the amount of latency that is desirable. For future research it should be looked into how RapidWright can place or route a design to further increase the throughput.
Item Type:Essay (Bachelor)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:53 electrotechnology, 54 computer science
Programme:Electrical Engineering BSc (56953)
Link to this item:https://purl.utwente.nl/essays/79103
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