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An Asynchronous Approach for Designing Robust Low Power Circuits

Yadav, Shubham (2019) An Asynchronous Approach for Designing Robust Low Power Circuits.

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Abstract:This thesis work investigates asynchronous design techniques for robust low power digital circuits. Asynchronous circuits can be an alternative to the widely-used synchronous design style as they can operate at very low voltages and are mostly immune to PVT (Process-Voltage-Temperature) variations. Asynchronous designs are also well known for their event-driven functionality where the power consumption is ideally zero while the design waits for an event. There are multiple handshaking protocols, design templates and transistor-level cell designs which contribute to a large design space for asynchronous designs. In this thesis work, this design space is studied and careful design decisions are taken at every step. A complete flow of circuit design is presented along with assumptions taken while exploring the design space. An unsigned 64-bit Kogge-Stone adder is taken as a benchmark design. The investigation focuses on achieving performance improvements (speed, power, etc.) as well as the use of design tools to evaluate performance. To perform a fair comparison, this 64-bit adder is also designed using the synchronous style and comparison results are presented.
Item Type:Essay (Master)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:53 electrotechnology, 54 computer science
Programme:Embedded Systems MSc (60331)
Awards:Cum Laude
Link to this item:http://purl.utwente.nl/essays/79740
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