University of Twente Student Theses


Streaming array modelling and generating VHDL with Python

Walle, R. C. M. van der (2019) Streaming array modelling and generating VHDL with Python.

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Abstract:This work presents the first working prototype of Streaming Array Modelling for Python (SamPy), a proposed concept to describe streaming systems in the commonly used programming language Python, as well as the development of a VHDL generator to generate VHDL code from a described streaming data system. The objective of this work is to overcome several problems introduced when working on large and complex streaming data systems. This includes the fact that communicating about such a system by the people involved can be rather difficult. SamPy enables a clear and organized way of describing these large systems, reducing the communication difficulty. Another issue is that system properties and stream definition are not directly related when using conventional methods. SamPy solves this by enabling programming in a stream-oriented way. The last problem addressed in this work is that the development of interfaces is very time consuming. This is improved by the realisation of the VHDL generator. This generator interprets a detailed SamPy system description and can generate complete hardware descriptions of pipelines to be implemented on FPGAs.
Item Type:Essay (Master)
Astron, Dwingeloo, Netherlands
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:53 electrotechnology, 54 computer science
Programme:Electrical Engineering MSc (60353)
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