University of Twente Student Theses
Design of a Digital Oversampling PLL
Westerdijk, B.P.J. (2020) Design of a Digital Oversampling PLL.
Full text not available from this repository.
| Full Text Status: | Access to this publication is restricted |
| Embargo date: | 31 August 2027 |
| Abstract: | In modern telecommunication systems the phase locked loop forms an integral part of the transceiver architecture. In these systems, it is used for clock recovery and frequency synthesis. For wideband-radio front-ends the PLL performance in terms of phase noise is one of the main limiting parameters. In this work a novel approach to generate a low-noise local oscillator signal using a wideband PLL architecture is presented. By using an oversampling phase-detector as a front-end, the loop bandwidth can be extended to frequencies beyond the reference frequency, allowing for a higher system performance, in terms of total local oscillator jitter to power ratio. An analysis has been performed with respect to power consumption of the proposed architecture and different implementations of this architecture have been compared with the relevant state of the art. |
| Item Type: | Essay (Master) |
| Faculty: | EEMCS: Electrical Engineering, Mathematics and Computer Science |
| Programme: | Electrical Engineering MSc (60353) |
| Link to this item: | https://purl.utwente.nl/essays/83803 |
| Export this item as: | BibTeX EndNote HTML Citation Reference Manager |
Show download statistics for this publication
Show download statistics for this publicationRepository Staff Only: item control page