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A High Throughput Sorting Accelerator using an Intel PAC FPGA.

Nijkamp, Bas (2022) A High Throughput Sorting Accelerator using an Intel PAC FPGA.

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Abstract:In this thesis we describe the development of an accelerator on the Intel Hardware Accelerator Research Program (HARP) platform. This platform provides tools and services to build FPGA based accelerators that work closely together with a GPP/CPU to optimize certain workloads. We focus on the design and development of a sorting accelerator.
Item Type:Essay (Master)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:54 computer science
Programme:Embedded Systems MSc (60331)
Link to this item:https://purl.utwente.nl/essays/90544
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