University of Twente Student Theses


Preventing soft-errors and hardware trojans in embedded RISC-V cores

Annink, E.B. (2022) Preventing soft-errors and hardware trojans in embedded RISC-V cores.

[img] PDF
Abstract:Single-event upsets and multiple-bit upsets that are part of single-event effects, cause bit-flips and hence lead to data corruption. Therefore, devices that are deployed in harsh environments such as in space use fault-tolerant processors or redundancy methods to ensure hardware reliability. Another serious vulnerability is the introduction of hardware trojans. Besides environmental side-effects, an adversary that has injected a malicious mechanism e.g., in the processor or memory can trigger unwanted behavior or leak sensitive information. Techniques to prevent or mitigate hardware trojans are important to ensure hardware security. Proprietary solutions exist in the market that introduces fault-tolerance or security extensions to establish this. Openness is important to prevent monopolistic proprietary solutions and create alternative solutions, such as an analogy of what happened in the world of Operating Systems; Windows NT (proprietary OS and kernel) versus Linux (open-source kernel). This is where the open RISC-V instruction set architecture becomes relevant. A novel solution to improve the security and reliability of RISC-V soft-cores with a low area and latency overhead was introduced in this thesis. The instruction validator which is the first part of this solution can effectively detect hardware trojans and multiple-bit upsets in the instruction memory by checking instruction/address pairs using a Bloom filter probabilistic data structure. The second part of the solution is the proposal of an error correction code instruction memory using Hamming single-error correction to detect and correct single-event upsets. It has also been proven that the Hamming decoder improves the detection performance of the instruction validator. An automation framework was introduced to generate, simulate and synthesize the instruction validator for different configurations which presents the designer with different options based on the application requirements. Besides this automation framework, two BF optimizations were proposed that decrease the BF area overhead. The instruction validator and error correction code instruction memory were successfully tested and integrated with the FreNox RISC-V core on an FPGA fabric. This resulted in a low area and latency overhead which makes it suitable to use with embedded RISC-V soft-cores that have strict security and reliability requirements.
Item Type:Essay (Master)
Technolution B.V., Gouda, the Netherlands
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:54 computer science
Programme:Embedded Systems MSc (60331)
Link to this item:
Export this item as:BibTeX
HTML Citation
Reference Manager


Repository Staff Only: item control page