University of Twente Student Theses
A comparison of the performance limitations of RC-, Shift Register- and Delay-locked loop- based multiphase clock generation schemes
Sanga, M. (2022) A comparison of the performance limitations of RC-, Shift Register- and Delay-locked loop- based multiphase clock generation schemes.
|
PDF
4MB |
| Abstract: | Multi-phase clock generators (MPCGs) are often used in wireless communication systems, high-speed serial links and other applications where high frequency clock signals are advantageous to system performance. As a result of their increasing importance in modern systems, various generation schemes exist. This paper analyses three generation schemes: Shift register- based MPCG (SR-MPCG), RC-based MPCG (RC-MPCG) and Delay-locked loop-based MPCG (DLL-MPCG). The paper begins by outlining the principles behind the operation of each scheme and proceeds to convey the observations and results from generating an 8-phase, 500MHz output signal using each scheme. All circuits are realised using 0.12μm MOSFET technology and 1.2V supply voltage. Finally, using phase accuracy and power usage as criteria, a cross-scheme comparison is made. The result of this comparison is that the SR-MPCG offers the highest level of phase accuracy and lowest power consumption. The DLL-MPCG had the lowest phase accuracy and the highest power consumption. |
| Item Type: | Essay (Bachelor) |
| Faculty: | EEMCS: Electrical Engineering, Mathematics and Computer Science |
| Subject: | 53 electrotechnology |
| Programme: | Electrical Engineering BSc (56953) |
| Link to this item: | https://purl.utwente.nl/essays/92373 |
| Export this item as: | BibTeX EndNote HTML Citation Reference Manager |
Show download statistics for this publication
Show download statistics for this publicationRepository Staff Only: item control page