Designing 8-bit approximate multipliers for FPGA using internal self-healing

This paper uses a design methodology for 8-bit approximate multipliers for FPGA using the Internal Self-Healing (ISH) methodology from a reduced design space of 4-bit approximate multipliers. Approximate computing is an effective method to reduce power consumption or chip area at the cost of output quality. However, optimizations made for ASIC may not translate entirely to FPGA, due to architectural differences. This paper emphasizes the importance of designing specifically for FPGA systems and presents a methodology that reduces the design space, while still allowing for the discovery of high-quality designs. The results show that optimized 8-bit multipliers for area outperform some of the state-of-the-art designs. Although power-optimized designs encountered some issues, the paper proposes possible multipliers to challenge the current state-of-the-art. Area-optimized designs are discussed which challenge the state-of-the-art. This paper demonstrates the effectiveness of the ISH methodology for designing efficient and high-quality 8-bit approximate multipliers for FPGA, with potential applications in error-resilient computing.