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Transistor level implementation of a 4 phase input clock signal into an 8 phase output clock signal
Straalen, B.J.J. van (2024) Transistor level implementation of a 4 phase input clock signal into an 8 phase output clock signal.
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| Abstract: | A switching radio mixer can use a multi phase mixer to reject higher harmonics. Using 8 instead of 4 phases rejects more harmonics. An 8 phase mixer does require an 8 phase clock signal which is more complicated to generate then a 4 phase clock signal. This 8 phase clock can be generated from a 4 phase clock, this method will be compared to generating the 8 phase clock from a 2 phase clock in power consumption and speed. Both designs are windmill type clock dividers. The designs will first be explained on logic gate level, then implemented on transistor level using 180 nM MOSFETs in LTspice. Dividing from 2 phases to 8 phases turned out more power efficient then dividing from 4 phases, because dividing from 4 phases requires 3 input logic gates instead of 2 input logic gates, which are used when dividing from 2 phases. |
| Item Type: | Essay (Bachelor) |
| Faculty: | EEMCS: Electrical Engineering, Mathematics and Computer Science |
| Subject: | 53 electrotechnology |
| Programme: | Electrical Engineering BSc (56953) |
| Link to this item: | https://purl.utwente.nl/essays/98467 |
| Export this item as: | BibTeX EndNote HTML Citation Reference Manager |
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