Design and Evaluation of a Flexible, Loop-Optimized, Sparse Co-Processor for Energy-Efficient RISC-V-based Neuromorphic Systems

The field of neuromorphic computing has aimed to design energy-efficient accelerators to address the rapid growth in energy consumption of AI models. Recent work has composed neuromorphic cores of both RISC-V processors and dedicated accelerators to ensure both flexibility and efficiency in terms of throughput and energy consumption. This work aims to optimize dedicated accelerators for RISC-V-based neuromorphic systems to improve their throughput and energy efficiency. To achieve the optimizations, an analysis is made of the fundamentals of neural networks along with the trade-offs and innovations of existing accelerators. An instruction set architecture is designed to efficiently represent the main computational operations of convolutional neural networks. The proposed co-processor is composed of a loop-optimized controller to exploit the recurrent patterns of neural networks and of a parallel array of processing elements that employ low-precision integer-only arithmetic. The level of quantization is based on a trade-off between computational efficiency and model accuracy. Finally, this work proposes two novel architectures to exploit weight sparsity in RISC-V-based neuromorphic systems. The co-processor is evaluated against a standalone RISC-V processor with VGG-16. Without exploiting weight sparsity, the co-processor achieves a speedup of 67x to 79x and a reduction in energy consumption of 22x to 28x over a standalone RISC-V processor at a cost of a 2.38% increase in area. At a weight sparsity of 80-86%, the co-processor achieves a speedup of 120x to 138x and a reduction in energy consumption of 53x to 61x over a standalone RISC-V processor at a cost of a 2.65% increase in area. The co-processor offers a competitive balance between area, energy efficiency, throughput, and flexibility compared to existing accelerators for RISC-V-based neuromorphic systems. As such, this work provides architectural decisions and quantifies their impact on the competitiveness of neuromorphic systems. In addition, this work identifies key bottlenecks and outlines possible improvements to increase the throughput and efficiency of accelerators for RISC-V-based neuromorphic systems.