Mapping dataflow over multiple FPGAs in Clash

This thesis will explain how (Homogenous) Synchronous Dataflow ((H)SDF) graphs can be mapped over multiple FPGAs. This is implemented in Clash, a functional hardware description language that can transform High-level descriptions to low-level synthesizable VHDL, Verilog or SystemVerilog. It has been implemented in such a way that it is deterministic and that over the found implementation, for some examples, a timing analysis is done. So, the desired (H)SDF graph and the implemented one can be studied.