A minimal nanoneuron capable of nonlinear classification

This paper addresses the challenge of optimizing neuromorphic computing hard- ware by investigating Dopant Network Processing Units (DNPUs). To circumvent the costs and labor-intensive nature of direct fabrication of these devices, we leverage com- puter simulations and machine learning techniques. Utilizing results from Theuws, we train a surrogate model via machine learning to study the behavior of the smallest theoretically feasible DNPU. Our analysis focuses on the device’s stability, robustness, and its ability to implement Boolean functions, with an emphasis on the non-linear XOR gate. The results demonstrate that DNPUs can efficiently perform complex com- putations with minimal size parameters, promising their potential for energy-efficient neural network hardware.