Harnessing FPGAs for Cost-Effective Cracked Egg Detection with OVONAS

In the egg grading industry machine learning is on the rise, with multi GPU systems being deployed worldwide. This study explores the applicability of Field-Programmable Gate Array (FPGAs) as AI Accelerators for cracked egg detection as a more energy and cost effective system. Introducing OVONAS a Hardware-Aware Neural Architecture Search (HW-NAS) algo- rithm optimized for FPGA deployment with FINN. The FPGA- based solution developed through OVONAS achieved a crack detection rate (CDR) of 76%, a False Reject Rate (FRR) of 6%, throughput of 127 Chests Per Hour (CPH), with latency of 5.914 μs and a power consumption of 12 Watt. Falling short GPU performance in terms of CDR, FRR and throughput but reducing power consumption by 90%, reducing latency by 78% for single egg inference. Despite the current limitations in crack detection, FPGAs show promise for less demanding tasks like egg weight and contaminant detection, suggesting potential for future improvements and broader industry applications.