LLM-Driven FPGA Design: Automating and Optimizing Electronic System Design

Field-Programmable Gate Arrays (FPGAs) are essential in reconfigurable computing, but their design process remains labor-intensive, requiring expertise in Hardware Description Languages (HDLs) and Electronic Design Automation (EDA) tools. Recent breakthroughs in Large Language Models (LLMs), such as GPT-4, demonstrate their potential to automate complex tasks like code generation and optimization. This research investigates the integration of LLMs into FPGA design workflows, focusing on logic synthesis, placement, and routing. By developing a structured methodology, we aim to enhance design efficiency, reduce human intervention, and improve performance metrics (e.g., power efficiency, resource utilization). The study will validate the approach through simulations and benchmarks against a golden standard benchmark, contributing to the emerging field of AI-driven hardware design.