Efficient Network On Chip for a RISC-V based neuromorphic processor

Neuromorphic processors utilize distributed nodes for parallel and energy-efficient computations that are well-suited for neural network workloads. These nodes require a communication mechanism that is both low-overhead and simple, without compromising system performance. This thesis presents the design and evaluation of a power- and area-efficient Network on Chip (NoC) for neuromorphic processors. This NoC is designed for optimizing Power, Performance, Area (PPA) trade-offs while managing congestion and data transfer. To achieve these goals, the architecture employs a 2D mesh topology with input First In, First Out (FIFO) buffers, round-robin (RR) scheduling, a ready/valid handshaking protocol, store-and-forward packet switching, and dynamic XY routing. A First In, First Out (FIFO) depth of four and dynamic XY routing were selected to optimize performance under congestion. Experimental results show that the system achieves a throughput of one packet per clock cycle under non-congested conditions, with a measured propagation delay of four clock cycles. Power analysis reveals that the energy per packet is 296 fJ, and the idle power consumption of one node is 22μW . Optimal performance is achieved with a directional data flow, such as that of a neural network, which is due to the potential for cyclic dependencies introduced by the interaction of routing and flow control. The NoC interconnects NEORV32 processors optimized for event-driven Artificial Neural Network (ANN) computations. In this experiment, a standardized 4-by-4 NoC is deployed with different mapping strategies of the same ANN. Results show that the NoC contributes only 0.24% to the total area and between 2.9% and 5.2% to overall energy consumption. As the system becomes more parallel, a trade-off emerges between active communication overhead and performance gains.