Analysis and Rerouting of Nets for Partial Reconfigurable FPGA Designs using RapidSmith2

This work analyses the routing of partial reconfigurable modules and how this can be changed using the open-source tool RapidSmith2. This tool provides an important interface for projects created in Vivado. Furthermore, RapidSmith2 provides data structures that allow for the modification of individual cells and routes in the FPGA design. Using this tooling, it is possible to interfere in the normal design flow in order to analyse the interfaces of partial reconfigurable modules. Moreover, the tooling can be applied to identify nets crossing the border of these partial reconfigurable modules and re-route them using a simple algorithm. This has been performed and tested on a simple VHDL design to verify its operation. With this analysis, the paper provides a basic framework for the analysis of partial reconfigurable FPGA designs using RapidSmith2.