Design Reconstruction for Partial Reconfigurable FPGA Systems

This work proposes an automated tool for verification and design reconstruction for PR systems. The verification part checks if a given set of modules is compatible with each other and the static system. A fully placed and routed netlist is obtained by merging reconfigurable modules back into the static design. Since place and route constraints must be kept, the merge is done on a netlist level. The so-called design reconstructing takes care of this merge process. The logic of the modules that belong to a specific configuration is placed into the partial region of the static system and interface nets are reconnected. We end up with a fully placed and routed design on which a timing analysis and functional simulation can be performed.