A method for modeling the dominant parasitic behaviour of a chip interface as a RLC-network by fitting onto simulated s-parameters

This paper presents a method for modelling the dominant parasitic behaviour of a package interface for an n-path filter/mixer chip, as a lumped element equivalent circuit. 3D electromagnetic (EM) simulation software is used to model the interface geometry and extract the parasitic s-parameters. These parameters are used to fit a lumped element equivalent circuit, such that the difference between the s-parameters of the RLC-network and the EM simulation is minimised. The RLC-model enables estimation of the package performance and gives insight into the dominant parasitic behaviour of the package parasitics. The method can be generalized to model a wide variety of IC interfaces.