ClaSH-based Framework for Hardware Generation of Optimised Real-Time SDRAM Interfaces Using Static Memory Access Patterns

In real-time systems it is essential that the worst-case latency bound of each task is known. On FPGAs, designers have more control over the implementation such that determinism is easier to guarantee but inherently requires more development effort. A modular real-time framework is being design in the high-level hardware description language ClaSH to support designers. This framework lacks a memory interface for off-chip data storage and hence the research question of this thesis: How can design-time knowledge of memory access patterns be used to generate an optimised real-time memory interface using a framework in CaSH? This thesis aimed to create an analysable real-time memory DRAM interface with deterministic actively managed buffers.