Mapping Hardware Descriptions to Bittide Synchronized Multiprocessors for Instruction Level Parallelism

Efforts to enhance computational speed have been ongoing since the inception of processors. This research explores a way to program multiprocessors using HDL (Hardware Description Languages). A mapping has been created between HDL and synchronized multiprocessors, specifically bittide synchronized multiprocessors. The bittide network is a new approach to synchronize multiprocessors to allow for instruction-level parallelism. The central research question is Can the bittide network be programmed using hardware description languages (HDL) in a way that exploits the available parallelism? HDLs provide inherent fine-grained parallelism as the components in circuits lay physically next to each other and operate simultaneously. The bittide network provides the ability for instruction-level parallelism needed to exploit this fine-grained parallelism. In this research, an approach is successfully demonstrated which maps hardware to a DAG (Directed Acyclic Graph) of RISC-V instructions, which is then scheduled over a bittide network of RISC-V cores. A simulator has been implemented capable of simulating this network which was used to verify the correctness of the mapping. The mapping was able to find a high degree of parallelism in simple programs. 16x16 matrix multiplication requiring 8705 cycles on a single core could be executed in 95 cycles on a (slightly unrealistic) fully connected network of 100 RISC-V cores, meaning a 91x speedup.