University of Twente Student Theses

Login

Designing a RERI-based error logging system for RISC-V cores

Koenderink, Michiel (2025) Designing a RERI-based error logging system for RISC-V cores.

[img] PDF
3MB
Abstract:In recent years, the adoption of RISC-V cores in advanced systems has grown significantly. These cores are employed in several areas, including environments with a higher risk of hardware errors, such as space. Critical systems must be able to detect and resolve as many errors as possible to maintain reliable operation. Error detection, logging, analysis and resolution keep systems operational while collecting important diagnostic information. The RISC-V organisation proposed a specification for formatting error information, known as RERI. However, extensive and large nature of this format can be impractical where time and resources are scarce. Furthermore, no dedicated framework around this error logging format has been specified yet. This work builds on the initial RISC-V RERI specification by implementing an adapted version called ”RERI-Lite”. Developed primarily for research use in radiation beam experiments, this system addresses the needs of smaller scale applications with high error rates. This thesis focuses on the implementation of a RERI-Lite based system and it compares RERI-Lite to the standard RERI format. It demonstrates how the lighter, more flexible design of RERI-Lite improves performance in resource-constrained contexts. Finally, the philosophy behind the error logging framework is examined, illustrating how it fits into broader system reliability goals.
Item Type:Essay (Master)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:50 technical science in general
Programme:Embedded Systems MSc (60331)
Link to this item:https://purl.utwente.nl/essays/106155
Export this item as:BibTeX
EndNote
HTML Citation
Reference Manager

 

Repository Staff Only: item control page