University of Twente Student Theses
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How does post-synthesis timing analysis differ from post-layout timing analysis in a RISC-V processor implementation using open-source toolchains?
Visser, B.T. (2025) How does post-synthesis timing analysis differ from post-layout timing analysis in a RISC-V processor implementation using open-source toolchains?
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| Abstract: | The semiconductor industry's shift towards Domain-Specific Architectures (DSAs), largely enabled by the open RISC-V instruction set architecture, has complicated the choice between mature, proprietary electronic design automation toolchains and emerging open-source alternatives. A critical challenge in any physical design flow is optimization of Performance, Power, and Area (PPA). This challenge is further complicated by the “predictive gap”--the discrepancy between post-synthesis estimates and final post-layout PPA results. This thesis investigates the significance of this gap in an open-source toolchain and compares synthesis quality when implementing an identical RISC-V System on a chip using the open-source Yosys and the proprietary Cadence Genus synthesis tools. Both flows targeted the IHP 130~nm PDK. Post-synthesis analysis revealed that the proprietary tool produced a more efficient netlist, at the cost of a longer runtime. Critically, post-synthesis timing proved to be an unreliable predictor of final performance in the open-source flow; a design that met timing after synthesis exhibited significant timing violations after physical implementation. This was accompanied by an increase in power and area due to buffer insertion for the clock tree and hold-time fixing. The results highlight the trade-offs between the rapid iteration speed of current open-source tools and the refined optimization of mature, proprietary ones, while underscoring that the predictive gap remains a significant challenge. |
| Item Type: | Essay (Bachelor) |
| Faculty: | EEMCS: Electrical Engineering, Mathematics and Computer Science |
| Subject: | 53 electrotechnology |
| Programme: | Electrical Engineering BSc (56953) |
| Link to this item: | https://purl.utwente.nl/essays/107404 |
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