University of Twente Student Theses


Distributed HIL simulation for Boderc

Groothuis, Marchel (2004) Distributed HIL simulation for Boderc.

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Abstract:The Boderc project group (Beyond the Ordinary: Design of Embedded Real-time Control) at the Embedded Systems Institute in Eindhoven, is modeling various aspects of a copier/printer. Design choices made during the development of the copier/printer can be altered and simulated in their models. Validation of the results is hard with the real setup (the copier/printer). To be able to test parameter changes without difficult modifications of the real setup, an experimental Hardware-In-the-Loop (HIL) simulation setup is required. The goal of this Msc project is to build a distributed Hardware-In-the-Loop simulation setup. Hardware-In-the-Loop simulation involves connecting a real embedded control system (ECS) to a computing unit with a competent real-time simulation model of the controlled plant. This enables systematic and automated testing of the ECS. The search for suitable hardware together with the development of the required software is part of the project. The Communicating Threads (CT) library is used for the development of the ECS and HIL simulator software. The main focus for the HIL simulation setup was on the realization of a distributed ECS and the I/O interface. An important component of the HIL simulation setup is formed by the boundary between the ECS and the HIL simulator. Research has been performed on the requirements and possibilities for the I/O interface between ECS and HIL simulator. On the basis of the results, a choice was made for a FPGA based digital I/O board useable for both the ECS and the HIL simulator for low- and high speed signal generation. To use the board for the ECS and the HIL simulator, a FPGA configuration is created that provides the ECS with PWM outputs, encoder inputs, clock frequency outputs and general purpose I/O. The FPGA configuration provides the HIL simulator with a complementary I/O interface that can be connected directly to the ECS. The realized ECS setup consist of four embedded PC/104 PC's connected to each other via a CAN field bus. The PC's are equipped with a custom-made embedded Linux installation with RTAI/LXRT real-time extensions. The setup uses two 20-sim code generation templates for the generation of the controller and HIL simulation software. The generated software uses the CT library together with LXRT. A set of new communication linkdrivers is written to provide channel based communication over the CAN bus and TCP/IP sockets, using the new remote linkdriver concept. New CT I/O linkdrivers are written to provide access to the parallel port hardware and to the outputs of the FPGA I/O board. The distributed ECS setup is able to demonstrate the principle of HIL simulation using the Linix setup as test case. It is possible to disconnect the real Linix setup from its controller and to plug in a HIL simulator with a model of Linix setup without any modification of the controller software and hardware. The resulting controller signals are equal to the simulation results. During the implementation of the various linkdrivers and CT programs, it turned out that the CTC(++) library has some important shortcomings that should be solved in future versions. The current library has no support for timing under Linux which makes it difficult to develop control applications that should run with a specific sample rate. A combination with RTAI/LXRT can solve this issue. A second problem is related to the use of system calls, which block the entire CT program instead of only the calling process. Each CT should be mapped on a separate operating system thread to solve this problem in the future.
Item Type:Essay (Master)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:53 electrotechnology
Programme:Electrical Engineering MSc (60353)
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