Design of clock cleaner : a fast locking PLL

Griffioen, H.T. (2008) Design of clock cleaner : a fast locking PLL.

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Abstract:Today's communication systems make use of a variety of phase-locked loops (PLL), for instance in burst wise digital audio. Clock/Data signals can be heavily distorted by jitter. Typically PLL's are used to suppress the jitter through their low loop bandwidth, but bring along long settling times as well. In comparison with the amount data to be sent, this settling time can become significantly large and not very power-efficient. In order to reduce this overhead, a new PLL has been developed. This PLL contains a frequency estimator which estimates the frequency within one period of the incoming clock signal. A switched capacitor relaxation oscillator has been used in order to integrate the estimator with the VCO of the PLL. This avoided the need of calibration of those two building blocks. The results are a PLL which can lock within 4 clock periods of the incoming clock. At 6:67MHz this is equal to 600ns, which is remarkably fast. It is expected that this can even be faster with only one clock period.
Item Type:Essay (Master)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:54 computer science
Programme:Computer Science MSc (60300)
Link to this item:http://purl.utwente.nl/essays/58403
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