Streaming reduction circuit for sparse matrix vector multiplication in FPGAs

Gerards, M. (2008) Streaming reduction circuit for sparse matrix vector multiplication in FPGAs.

[img]
Preview
PDF
521kB
Abstract:In this thesis an algorithm is introduced that uses 5 simple rules to check in which order values have to be reduced using a single associative and commutative binary operator.
Item Type:Essay (Master)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:54 computer science
Programme:Computer Science MSc (60300)
Link to this item:http://purl.utwente.nl/essays/58410
Export this item as:BibTeX
EndNote
HTML Citation
Reference Manager

 

Repository Staff Only: item control page