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Increasing the spurious-free dynamic range of an integrated spectrum analyzer

Oude Alink, M.S. (2008) Increasing the spurious-free dynamic range of an integrated spectrum analyzer.

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Abstract:Spectrum Analyzers (SAs) are measurement instruments able to decompose a time signal into its frequency components. Due to non-idealities, SAs add noise and distort the signal to be measured. The ratio between the the largest signal and the noise floor level in a measured spectrum, without any distortion components rising above the noise floor, is called the Spurious-Free Dynamic Range (SFDR). In a CMOS-integrated SA the SFDR is limited to around 60 dB by technology, while it needs to be 70 dB (at a frequency resolution of 1 MHz) to be competitive with commercial SAs. A method called crosscorrelation is introduced to lower the noise floor at the cost of measurement time. It relies on two equivalent measurement paths in which the noise produced in one path is uncorrelated with the noise produced in the other path, such that the noise in the final spectrum tends to cancel out. Although the noise level is only lowered by 1:5 dB if measurement time is doubled, it allows the SA to be designed for high linearity. This design involves the use of digital hardware to compute the crosscorrelation. Consequently Analog-to-Digital Converters (ADCs) are required, but they also limit the SFDR due to the non-linear eect of quantization. New approximations to the relation between the number of quantization levels and the SFDR are found. These approximations show that very additional bit improves the SFDR by 8 dB. A simulator of a concept architecture from Recore Systems is used to implement the digital correlation. It achieves an SFDR of 87 dB. An RF-frontend with a frequency range of 0 GHz to 6 GHz is designed for maximum linearity by moving amplification to IF. It provides impedance matching, variable attenuation and mixing. Its performance gures are a Noise Figure (NF) of 14 dB and a Third Order Input-referred Intermodulation Intercept Point (IP3) of +23 dBm, which gives a theoretical SFDR of 82 dB. In order to obtain estimates on the feasability of an integrated SA, other parts, such as the IF-circuitry and local oscillators, are briefly reviewed. The estimated power consumption of the entire correlation SA is 0:5 W at a sample rate of 200 MS/s, and the estimated chip area is 6:5 mm2. The largest power consumers are the VCO (0:2 W), followed by the IF-circuitry (0:1 W) and the ADCs and digital correlator (each 0:08 W). Chip area is dominated by SRAM-memory (36%), ADCs (25%) and the VCO (20%)
Item Type:Essay (Master)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:54 computer science
Programme:Electrical Engineering MSc (60353)
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