Memory optimizations on the sequential hardware-in-the-loop simulator

Simulating hardware designs with the assistance of a Field-programmable Gate Array (FPGA) can greatly increase the simulation speed. Especially since new hardware designs often encompass a complete System-on-Chip (SoC). Due to the limited resources of a single FPGA these designs may be too large to instantiate them into an FPGA. Wolkotte et al, presented a simulation approach that can simulate those designs [1]. The approach uses time multiplexing to simulate only a small part of the hardware designs in a single clock cycle. This technique works well with hardware designs that contain a lot of nearly identical components, e.g. a Multi Processor System-on-Chip (MPSoC). Such a MPSoC may consist of a 2d-mesh Network-on-chip (NoC). Each router in the NoC could be connected to a small processing element, i.g. the Montium tile processor [2]. One of the transformations that is performed for time multiplexing the simulation is state extraction. The current approach by Rutgers [3, 4] is only able to extract flip-flops from the hardware designs. This thesis introduces some new algorithms that extract large memories. These algorithms make it possible to also simulate the network with the processing element attached. This was not possible in the approach of Rutgers due to the bandwidth limitations within an FPGA.