Low series resistance structures for gate dielectrics with a high leakage current

Over the succession of chapters, this master thesis describes: 1. the consequences of the gate oxide shrinkage on electrical device characterization, a major issue concerns the large tunneling currents through the oxide and a relatively high value of the series resistance. Reciprocally, these parameters are related to the device performance. 2. the approach to successfully handling these issues, 3. a solution that should allow an accurate characterization. Radio frequency (RF) test structures are designed from which a capacitancevoltage (C-V ) curve can be obtained. Electrical device parameters can be extracted from the intrinsic RF C-V curve by using a simulation model