University of Twente Student Theses


A dataflow architecture for beamforming operations

Wester, Rinse (2010) A dataflow architecture for beamforming operations.

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Abstract:As current radio telescopes get bigger and bigger, so does the demand for processing power. General purpose processors are considered infeasible for this type of processing which is why this thesis investigates the design of a data ow architecture. This architecture is able to execute the operations which are common in radio astronomy. The architecture presented in this thesis, the FlexCore, exploits regularities found in the mathematics on which the radio telescopes are based: FIR filters, FFTs and complex multiplications. Analysis shows that there is an overlap in these operations. The overlap is used to design the ALU of the architecture. However, this necessitates a way to handle state of the FIR filters. The architecture is not only able to execute data ow graphs but also uses the data flow techniques in the implementation. All communication between modules of the architecture are based on data flow techniques i.e. execution is triggered by the availability of data. This techniques has been implemented using the hardware description language VHDL and forms the basis for the FlexCore design. The FlexCore is implemented using the TSMC 90 nm technology. The design is done in two phases, first a design with a standard ALU is given which acts as reference design, secondly the Extended FlexCore is presented. The Extended FlexCore incorporates the ALU which exploits the regularities found in the mathematics. The ALU of the Extended FlexCore is able to perform a four point FIR filter, a complex multiplication or an FFT butterfly operation in a single clock cycle. The Extended FlexCore uses an Explicit State Store (ESS) to handle stateful operations like a four point FIR filter. The standard FlexCore and the Extended FlexCore are compared by executing a FIR filter, FFT and complex multiplications. The comparison shows that the Extended FlexCore is significantly more energy efficient per operation than the reference FlexCore. Finally, an indication of the energy efficiency of the Extended FlexCore is given in comparison with other architectures. It is shown that the FlexCore lies, in terms of energy per operation, between the ASICs and the general purpose ARM processor.
Item Type:Essay (Master)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:54 computer science
Programme:Computer Science MSc (60300)
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