Design of a Fused Multiply-Add Floating-Point and Integer Datapath

Bruintjes, Tom M. (2011) Design of a Fused Multiply-Add Floating-Point and Integer Datapath.

Abstract:Traditionally oating-point and integer arithmetic have always been separated both spatially and con- ceptually. Even though the oating-point unit is an integral part of most contemporary microprocessors, it uses its own dedicated set of arithmetic components. Due to the high data width of oating-point numbers, these arithmetic components occupy a signi�cant percentage of the silicon area needed for a processor. Low-cost and low-power driven processor design, which is becoming increasingly more impor- tant due to the ever growing market for battery-operated hand held devices and the need for sustainable usage of energy resources, are therefore di�cult targets for oating-point arithmetic. In this thesis we present a solution in the form of a new architecture that combines integer and oating- point arithmetic in a single datapath. Both types of arithmetic are tightly integrated by mapping functionality to the same basic hardware components (the multipliers, adders, comparators etc.). The advantage of such an approach is two-fold. Because the oating-point unit can be scheduled for integer instruction, we are able to cut-down on integer dedicated resources making oating-point units justi�- able in a low-cost environment. Additionally, the hardware needed for oating-point arithmetic can be used much more e�ciently, because in realistic scenarios then the amount of oating-point instructions performed is much less that a typical oating-point unit can process. The architecture we present is tailored for a minimal silicon area and energy-e�ciency. However, perfor- mance also remains an important factor. A particularly powerful architecture known as fused multiply- add (FMA) is chosen as the base for a oating-point unit with integrated integer functionality. Besides higher throughput, the added value of oating-point fused multiply-add (A�B+C) is higher accuracy, a result of the fact that only a single rounding operation is performed per instruction. From an area conser- vative point of view, FMA is also eligible. Instructions such as multiplication and addition/subtraction can simply be derived by using 0 and 1 for the addend (C) and multiplicand (B) respectively, hence there is no need for hardware that implements basic multiplication and addition. The architecture is further optimized for area e�ciency and performance by using smart design principles like Parallel Alignment, Partial Product Multiplication, End-Around Carry Addition, Leading Zero Anticipation, Leading Zero Detection and high component re-use. The leading zero detection circuit is worth mentioning explicitly. A new approach based on earlier work [1] is presented that yields much better area (up to almost 50% reduction) for input that is not a power of two. The resulting design is a balanced three stage pipeline with considerable integer re-use. The oating- point arithmetic is numerically compliant with IEEE-754, based on a 41-bit (8-bit exponent and 32- bit signi�cand sign-magnitude) oating-point representation. Integer arithmetic is performed in 32-bit signed two's complement format. As a proof of concept, a VHDL structural description is implemented in STMicroelectronics 65nm technology. A performance driven implementation reaches a theoretical peak bandwidth of 2.4 GFLOPs at 1200MHz, and a low-power implementation yields a circuit that can be clocked at a maximum frequency of 500MHz. Post synthesis/place-and-route estimates of area and power consumption are provided. Comparisons with other architectures and a realistic scenario for system-on-chip (SoC) integration show that the architecture is suitable for low-cost energy-e�cient hardware solutions.
Item Type:Essay (Master)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:54 computer science
Programme:Computer Science MSc (60300)
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