Design of a Fused MultiplyAdd FloatingPoint and Integer Datapath
Bruintjes, Tom M. (2011) Design of a Fused MultiplyAdd FloatingPoint and Integer Datapath.

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Abstract:  Traditionally oatingpoint and integer arithmetic have always been separated both spatially and con ceptually. Even though the oatingpoint unit is an integral part of most contemporary microprocessors, it uses its own dedicated set of arithmetic components. Due to the high data width of oatingpoint numbers, these arithmetic components occupy a signi�cant percentage of the silicon area needed for a processor. Lowcost and lowpower driven processor design, which is becoming increasingly more impor tant due to the ever growing market for batteryoperated hand held devices and the need for sustainable usage of energy resources, are therefore di�cult targets for oatingpoint arithmetic. In this thesis we present a solution in the form of a new architecture that combines integer and oating point arithmetic in a single datapath. Both types of arithmetic are tightly integrated by mapping functionality to the same basic hardware components (the multipliers, adders, comparators etc.). The advantage of such an approach is twofold. Because the oatingpoint unit can be scheduled for integer instruction, we are able to cutdown on integer dedicated resources making oatingpoint units justi� able in a lowcost environment. Additionally, the hardware needed for oatingpoint arithmetic can be used much more e�ciently, because in realistic scenarios then the amount of oatingpoint instructions performed is much less that a typical oatingpoint unit can process. The architecture we present is tailored for a minimal silicon area and energye�ciency. However, perfor mance also remains an important factor. A particularly powerful architecture known as fused multiply add (FMA) is chosen as the base for a oatingpoint unit with integrated integer functionality. Besides higher throughput, the added value of oatingpoint fused multiplyadd (A�B+C) is higher accuracy, a result of the fact that only a single rounding operation is performed per instruction. From an area conser vative point of view, FMA is also eligible. Instructions such as multiplication and addition/subtraction can simply be derived by using 0 and 1 for the addend (C) and multiplicand (B) respectively, hence there is no need for hardware that implements basic multiplication and addition. The architecture is further optimized for area e�ciency and performance by using smart design principles like Parallel Alignment, Partial Product Multiplication, EndAround Carry Addition, Leading Zero Anticipation, Leading Zero Detection and high component reuse. The leading zero detection circuit is worth mentioning explicitly. A new approach based on earlier work [1] is presented that yields much better area (up to almost 50% reduction) for input that is not a power of two. The resulting design is a balanced three stage pipeline with considerable integer reuse. The oating point arithmetic is numerically compliant with IEEE754, based on a 41bit (8bit exponent and 32 bit signi�cand signmagnitude) oatingpoint representation. Integer arithmetic is performed in 32bit signed two's complement format. As a proof of concept, a VHDL structural description is implemented in STMicroelectronics 65nm technology. A performance driven implementation reaches a theoretical peak bandwidth of 2.4 GFLOPs at 1200MHz, and a lowpower implementation yields a circuit that can be clocked at a maximum frequency of 500MHz. Post synthesis/placeandroute estimates of area and power consumption are provided. Comparisons with other architectures and a realistic scenario for systemonchip (SoC) integration show that the architecture is suitable for lowcost energye�cient hardware solutions. 
Item Type:  Essay (Master) 
Faculty:  EEMCS: Electrical Engineering, Mathematics and Computer Science 
Subject:  54 computer science 
Programme:  Computer Science MSc (60300) 
Link to this item:  http://purl.utwente.nl/essays/61055 
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