University of Twente Student Theses


Model based testing of a PLC based interlocking system

Hoeve, Thijs ten (2012) Model based testing of a PLC based interlocking system.

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Abstract:Interlocking systems control all wayside elements in a railway yard. These systems are responsible for safe train operations and must prevent collisions and derailments from happening. It is absolutely essential that interlocking systems operate awlessly, and as a result a lot of effort is put in their verification. ProRail (the Dutch railway infrastructure manager) is developing a new type of interlocking system based on off-the-shelf PLC hardware, the PLC- Interlocking. This report introduces a conformance testing methodology for PLC-Interlocking systems that is based around the JTorX test tool. The test method has been applied to the first instance of a PLC-Interlocking system, which is installed at the Santpoort Noord station. To get an SUT that can be tested, the interlocking logic is integrated in a program that adds interfacing code and is then recompiled for a regular PC system. As a result, testing does not require access to the PLC hardware. A number of test purpose models have been created to direct test case generation. These test purpose models were implemented in Java, using a custom framework that creates an LTS representation of inputs and outputs and handles communication with JTorX. A partial specification model has been implemented in mCRL2. Because of the complexity of the requirements and the limited available time, it was not possible to create a complete model. In fact, the complexity of the requirements has led to faults in the partial model that was implemented. The created test setup allows automated testing of the interlocking logic of PLC-Interlocking systems. The entire test setup can be run on a regular PC system, but is not very memory efficient. Of 73 automated test runs that were conducted, 36 ended with the observation of a failure. Four of these failures must be further investigated, but it seems likely that all failures were caused by faults in the model. The quality of the model is poor, as shown by the many failures that resulted from faults in the model. As a result, the quality of the whole test setup is not at a level where
Item Type:Essay (Master)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:54 computer science
Programme:Computer Science MSc (60300)
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