Designing a Low Noise Amplifier for Satellite Receivers in CMOS technology

Faber, T.D. (2007) Designing a Low Noise Amplifier for Satellite Receivers in CMOS technology.

Abstract:P.H.Woerlee et al. have demonstrated that due to downscaling the noise performance is improving. Calculations and simulations have been carried out to study the viability of a CMOS LNA, suitable for satellite receivers, in the current CMOS technology of 65 nm. The used low noise amplifier (LNA) can be represented by a common source transistor (CS), based on the work of K. Shaeffer and T. Lee [4][5][6]. A common source transistor can be described by four main noise parameters (Gu, Gc, Bc, Rn) and two source parameters (Gs, Bs). The source parameters can be designed such that the minimum noise performance (Fmin) can be reached. An analytical model, based on the four noise parameters, is compared with simulation results. Despite some small differences the predictions of the CS model resemble the simulation model. The model gives design insight and it is used to find the best design for low noise performance. The final and best design for low noise performance, having a noise figure of about 1 dB consists of a common source and cascode transistor together with a gate and drain inductance with a quality factor higher than 10. If a reasonable or good power match is desired an additional source inductance can be added, though the noise performance increases to just above 1 dB.
Item Type:Essay (Master)
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:53 electrotechnology
Programme:Electrical Engineering MSc (60353)
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