University of Twente Student Theses


A basis for the next VHDL revision

Jong, Berend J.M. de (2014) A basis for the next VHDL revision.

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Abstract:Over the years, the number of transistors that is available to hardware designers has exponentially increased. Because of this it is very important to have an effective hardware description language. One of the most important hardware description languages is the VHSIC hardware description language (VHDL). To cope with the increased number of transistors one could ask the question: "What language constructs can be added to the VHSIC hardware description language to keep it effective and relevant for the future?". To answer this question, a basic understanding of how compilers work is needed. The compiler starts by lexing files and then parsing the output of the lexer into an abstract syntax tree. Once the abstract syntax tree is made it can be traversed. Also a good understanding of how simulation- and synthesis-tools work is important. Simulators work with two types of events: timed events and delta events. The timed events cause signal changes and each timed event is followed by one or more delta events to bring the system back into a stable state. Synthesis tools are less predictable than simulation tools, since it is not always clear what exact gate level description the synthesis tool will come up with. The language enhancements that have been added to the language are: An independent compilation order of the input files, having no separation between the declaration area and the body area of architectures, subprograms, entities and blocks, being able to assign signals immediately after declaring them, being able to overload the assignment operator so less type transformation functions are needed, having namespaces that encapsulate all language elements and a new and fast attribute system. To be able to use these enhancements, a compiler is created that can compile the language with enhancement, back to the VHDL 2008 standard. The compiler uses five passes. During the first pass the VHDL files are linked and parsed. In the second pass all the declaration elements are collected. During the third pass these elements are linked together. In the fourth pass the expressions are reparsed since they are context sensitive. Finally the output of the compiler is generated during the fifth pass. Next the compiler is tested with a use-case design of Astron. With some small changes, the design can be compiled with the new compiler, and can be tested with the test-bench that was also provided by Astron. After this, parts of the code have been rewritten with the new language constructs and the output was tested successfully with the same test-bench. A multi-pass compiler gives a lot of freedom in terms of what can be added to the language. We can conclude that the new features improve the language, but that they are hard to implement on the existing compilers. In general the conclusion can be made that due to the design of the VHDL language it is hard to add new features to it.
Item Type:Essay (Master)
Astron, Dwingelo, Netherlands
Faculty:EEMCS: Electrical Engineering, Mathematics and Computer Science
Subject:54 computer science
Programme:Embedded Systems MSc (60331)
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